1. Field of the Invention
The invention relates to a tiny ball grid array package, and more particularly, to a tiny ball grid array package with an improved thermal and electrical performance.
2. Description of the Related Art
In an integrated circuit, signal lines formed upon the silicon substrate to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. The integrated circuit is then secured within a protective semiconductor device package. Each of the I/O pads of the chip is then connected to one or more terminals of a device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires are typically used to connect the I/O pads of the chip of the terminals of the device package. Some types of device packages have terminals called pins for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called "leads" for attachment to flat metal contact regions on an exposed surface of a PCB.
As the semiconductor technique has been updated with an increasingly higher integration and speed, the fabrication technique with a linewidth of about 0.18 micron has been achieved in mass production. The objective of being "compact, thin and light", has been a leading trend for the development of various aspects of semiconductor fabrication, including package technique. In addition, in view of operating an electronic device with increasingly higher operating speed, how to comply with the effect caused by the improved high frequency in package and how to improve heat dissipation are important topics in factory, as well.
FIG. 1 shows a schematic, cross-sectional structure of a conventional lead on chip package. The lead on chip package is commonly applied in a thin small outline package (TSOP). The lead on chip package uses a lead frame 24, which has a different structure from normal lead frames. The lead frame 24 comprises only multiple leads 10. A chip 12 has a surface 14 comprising bonding pads 16 which surface 14 is directly adhered onto the leads 10 using, for example, a double adhesive polyimide tape 18. The bonding pads 16 are disposed in positions on the surface 14 and near central portion of the surface 14. Each bonding pad 16 is coupled to one conductive wire 20 and a lead 10. A package material 22 encloses the chip 12, the conductive wire 20, and the connecting regions between leads 10 and bonding pads 16. In the lead on chip package structure, the usage of die pad is saved to result in a reduced package area and volume. By directly adhering the chip to the leads, a better heat dissipation path is provided. However, due to restriction imposed by a pitch inherent to the lead frame, it is difficult to effectively reduce the package size for high pin count devices. It is also difficult to resolve the high frequency inductance effect.
FIG. 2 shows a schematic, cross-sectional view of another conventional lead on chip package. The package structure shown in FIG. 2 is also called a tiny ball grid array or a thin and fine ball grid array. A ball grid array substrate is used as a carrier. A single layer of a ball grid array substrate 34 laminated with an inner layer of resin 30 and a copper foil 32 is used in the conventional structure. The inner layer 30 has an aperture 42 near a center thereof. The copper foil 32 is disposed on a surface 40 of the inner layer 30, and patterned into conductive traces 31. A surface 14 comprising bonding pads 16 of the chip 12 is adhered onto another surface 38 of the inner layer 30 using adhesive 44. The bonding pads 16 are formed on the chip 12 near a center thereof. When the chip 12 and the inner layer 30 are adhered to each other, the bonding pads 16 are aligned with the aperture 42. When a bonding process is performed to connect the bonding pads 16 and a near end 31a of the conductive trace 31 with bonding wires 20 going through the aperture 42. The connection of the bonding wires 20 and the conductive trace 31a is then sealed in a package material 22 to protect the adhering parts of the chip 12 and the ball grid array substrate 34. A far end 31b of the conductive trace 31 has another terminal having solder balls 36 disposed thereon to provide a connection to an external circuit, for example, such as a terminal for transferring a signal to a printed circuit board.
The above lead on chip package structure uses a ball grid array substrate instead of a conventional lead frame to reduce the pitch and size. However, heat is mainly generated from a surface comprising semiconductor devices which is taped with an inner layer, so that the effect heat dissipation is poor and degrades the performance of products. To effectively resolve the problems of heat dissipation, a heat sink is required on the chip to increase the cost of products. On the other hand, since the pitch between wires is smaller, the inductance effect is more obvious for a high frequency operation. The interference of signal becomes more serious and degrades the performance of products.